Register-Transfer Level (RTL) Integration engineers design the collective integration of codes written for chip partitions.
You will be responsible for the RTL integration of one or more IPs/subsystems into the server SoCs, starting with tech readiness through RTL1.0 and tape-in.
Technology readiness (TR) work will include assessing new IPs/features, TFM proposed changes design effort/complexity, and more. You will ensure that the incoming SIPs/HIPs you are responsible for meet the quality expectations for each SoC milestone and stay on SoC design schedules.
As an RTL Integration engineer, you will help integrate codes describing functionalities at the System on Chip (SoC) level. This role involves close interaction with the architecture team as it is a critical step for the physical design of the chip. The preparation of the netlist, which describes the components and connections of the circuit, depends on the integration of the codes.
We look for candidates with experience in IC/SoC design, as well as experience integrating internal or third party IPs into SoC products. You will also be responsible for milestone and paranoia checklist reviews and post-Silicon debug support. You get the opportunity to work on top technical projects with an excellent team of highly technical and collaborative engineers. You will bring your technical and leadership skills and be involved in the growth of a global company.