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Job ID: JR0171881
Job Category: Engineering
Primary Location: Guadalajara, JAL MX
Other Locations:
Job Type: Experienced Hire

Pre-Si Verification Engineer

Job Description

You will be responsible for the full life-cycle of verification, from planning to test execution and including collecting and closing coverage. You will closely interface with architecture and design teams to understand design/product requirements and develop comprehensive test plans and you will conduct/participate in test plan and test reviews, develop verification components and tests, and triage failures.

You will mentor and provide guidance to junior verification engineers in the execution of their tasks.

Responsibilities include:

  • Developing pre-Silicon functional validation tests to verify system will meet design requirements.
  • Creating test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests.
  • Analyzing and using results to modify testing.
  • The leader in this position develops scoreboard, monitors, checkers for IP.
  • Debug failing signatures.
  • Analyzes coverage holes to reach 100% functional coverage.
  • Reviewing test plans for all the IP blocks and tracking progress to milestones.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum qualifications:

  • Bachelor Degree in Computer Engineering or Electrical Engineering; 4+ years of experience in pre-Silicon verification
  • Experience: Relevant ASIC design/validation experience in front end processes including RTL development, functional and performance verification.
  • Expertise in verification of design blocks (IP) for system-on-chip (SoC) components.
  • Expertise in system Verilog , UVM, and/or OVM based verification methodologies.
  • Experience in OOP concepts, coverage based random validation.
  • Knowledge of scripting.
  • Developing scalable and portable test bench.
  • Waveform debugging with latest EDA tools, root-cause bugs independently.
  • Advanced English level.

Preferred qualifications:

  • Master or Phd degree in Computer Engineering or Electrical Engineering is a plus and counted as experience if related to the area.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

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