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Job ID: JR0205829
Job Category: Engineering
Primary Location: Phoenix, AZ US
Other Locations: US, California, Santa Clara;US, Oregon, Hillsboro;US, Texas, Austin
Job Type: Experienced Hire

Structural Design Engineer for Test Chip Development

Job Description

The world is transforming – and so is Intel!  Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful!

The SOC Debug Engineer role has a single purpose which is to solve our most challenging product issues. SOC Debug Engineers work with our internal product teams (Manufacturing/Validation/Software) and our customer teams during critical escalations to rootcause systemlevel failures and/or anomalies directly impacting our customers or jeopardizing our committed timelines.

Responsibilities will include but not limited to:

  • Performing lowlevel and complex debug across multiple IP and system domains within a product, and will use their experience with/understanding of SOC design and architecture, Firmware, Bios and software to completely understand any issue and drive a resolution.
  • Drive innovative debug capability improvements through new Design for Debug (DFD), debug tools and scripts to continuously improve the debug discipline


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of experience - OR - Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 2+ years of experience with:

  • Synopsys or Cadence design (RTL to GDS) tools.
  • Synopsys-Primetime.
  • ICV or Calibre DRC/LVS Layout cleanup



Preferred Qualifications:

  • Experience with STA at both partition and SOC level
  • Strong analytical ability, problem solving and communication skills
  • Ability to work independently and at various levels of abstraction
  • Experience in Perl, TCL/Tk programming.
  • Experience with TFM (Tools, Flows, Methodology) Development

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, California, Santa Clara;US, Oregon, Hillsboro;US, Texas, Austin


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

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