Design verification engineer

The responsibilities include all phases of pre-silicon verification including but not limited to:

• Verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out
• Develop/run/debug tests in System Verilog
• Establish DV methodologies
• Test-plan developments
• UVM /OVM

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In addition to the qualifications listed below, the ideal candidate will also have:

• Detail oriented individual with strong technical and collaboration skills to perform to high standards in a highly efficient verification team
• Thoughtful and perceptive analytical skills
• A genuine curiosity for understanding the system
• Dedicated and committed to creative problem solving and getting things done
• Willing to work with cross functional teams

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor’s degree in Electrical Engineering (EE), Computer Engineering (CE), or Computer Science (CS) and 3+ years of relevant work experience OR a Master’s degree in Electrical Engineering (EE), Computer Engineering (CE), or Computer Science (CS) and an additional 2+ years of relevant work experience with:

• System Verilog
• Developing scalable and portable test-benches
• Verification methodologies and tools such as simulators or waveform viewers or build/run automation or coverage collection or gate level simulations

Preferred Qualifications:

• Experience with DDR

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Santa Clara;US, Oregon, Hillsboro

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.