SoC Design Engineer - Design Automation
As a SoC Design automation engineer, you will be overseeing the definition, implementation, verification and documentation for System on a Chip development.
The main tasks as a SoC Design Automation Engineer may include
- Developing, supporting and driving design construction, power optimization & formal verification flows and methodology for cell-based and/or transistor-based designs
- Driving solutions to perform RTL to GDS automation using Engineering Design Automation (EDA) tools and internal CAD tools
- Partnering with CPU design engineers to highlight issues, debug complex problems and develop innovative solutions for analysis, construction and verification flows
- Developing custom optimized solutions to address design requirements for latest technology nodes
- Provide technical direction by identifying gaps in current EDA solutions and drive enhancements through vendors
- Documenting and helping with guidelines/specs
You must possess the below minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates
Candidate must have a Bachelor's degree in Electrical or Computer Engineering or related field and 3+ years of experience with OR a Master's degree in Electrical and Computer Engineering or related field and 2+ years of experience with:
- Design principles and techniques in VLSI backend design custom circuit transistor design and or memory design
- UNIX Linux environments and Perl Tcl Shell Python scripting
- Expertise in RTL Verilog language and Unified Power Format
- Familiarity with backend design EDA tools Synopsys Cadence and or Mentor Graphics.
1+ years of experience with
Inside this Business Group
- Design Automation for CPUs or SOCs including formal verification logic equivalence checking of gate level and or transistor level designs RLS SPICE in advanced CMOS processes
- Industry standard Engineering Design Automation EDA VLSI tools from Synopsys Cadence in one of more of the following Timing Power optimization ECO Static Timing Analysis SPICE circuit simulation statistical variation analysis noise crosstalk OCV and or ERC flows
- Machine learning methods to solve complex problems dealing with automation of circuit design to aid in performance and power improvement
- Synopsys Cadence Tcl coding
The Devices Development Group (DDG) is a global organization focused on the development and integration of SOCs, critical IPs including Atom and chipsets that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
US, Oregon, Hillsboro
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.