Inside this Business Group
Minimum Qualifications: Must have a BS or MS in Electrical Engineering, Computer Engineering, Computer Science or related, and 8+ years of experience in RTL/Logic design on ASICs or FPGA IP blocks or SOCs using System Verilog RTL coding Preferred Skills: Experience with PCIe and/or CXL Demonstrable experience in logic design and writing RTL in SystemVerilog Familiarity with a range of internal and 3rd-party logic design tools Strong analytical ability, problem solving and communication skills Gate-level understanding of RTL and synthesis - i.e. understand how RTL looks like/behaves after it is synthesized into gates Experience using lab equipment such as logic analyzers, scopes, protocol analyzers and the ability to use them to debug issues Strong communication and team-work stills. Ability to work independently and at various levels of abstraction
The everyday contributions of the Intel Validation Engineering (iVE) team are essential to retaining/regaining Intel's product leadership. We validate, debug, and tune the newest designs and world-changing technologies that enrich the lives of every person on earth. We play a critical role in completing the PRQs of Intel products and in Intel's ability to deliver the annual technology platforms in our roadmap.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.