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Job ID: JR0180027
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations: US, Oregon, Hillsboro
Job Type: Experienced Hire

DFT Engineer

Job Description

Join Intel's centralized Design for Test Engineering Group.

In this role responsibilities include, although not limited to:

  • Develop and support design for test (DFT) structures
  • Determine design for test approaches and develop DFT architecture
  • Design and verify DFT structures for memories (MBIST), digital and analog circuitry
  • Perform scan synthesis
  • Create, simulate and verify automatic generated test patterns (ATPG)
  • Create functional tests and corresponding test patterns
  • Knowledgeable regarding failure mechanisms in silicon production and creating test algorithms
  • Support silicon bring up of test patterns
  • Perform diagnosis of test patterns on silicon and optimize test time



Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must possess a Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 1+ years experience -OR- a Masters degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with experience in the following:

  • RTL coding such as Verilog or SV
  • DFT (well versed with SCAN, ATPG, Memory test, or IO test)
  • DFT EDA tools, architecture or IP development, or silicon bring up

NOTE: This position is not eligible for employment-based visa/immigration sponsorship for those with a Bachelor’s degree and less than 3 years of experience. Intel sponsors individuals for employment-based visas for positions where we experience a shortage of US Workers. These skills shortage roles are typically STEM contributing positions requiring a Master's or PhD degree, or a Bachelor’s degree with three years’ related job experience.

Preferred Qualifications:

  • 3+ years' experience in RTL environments and/or silicon design
  • Fault grading experience
  • Experience with DFT concepts
  • Experience supporting multiple design teams and understanding SOC design flows
  • Good SW skills using Perl, TCL, C++, etc.

Inside this Business Group

The Product Enablement Solutions Group (PESG) is a worldwide organization that delivers an end-to-end design system for development of IPs, Cores and SOCs. This business group partners with the Semiconductor, IP and EDA eco-systems and leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to deliver a world-class design system that powers Intel’s leadership products.

Other Locations

US, Oregon, Hillsboro

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

USExperienced HireJR0180027
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