In this role, the Senior Digital Physical IC Design Engineer will be part of team contributing to Silicon Photonics Solution Group's mission to transform and lead datacenter connectivity and enable Intel's differentiation in the networking space. As a senior Engineer, the individual will be involved in challenging projects and drive it to completion in record time. You will quickly ramp on the existing flow, understand the challenges, and produce the work plan. Your expertise in deep submicron technology, processor design, and teamwork skills will be highly leveraged to guide activity across the entire cross-discipline, multi-site team. You will work with others to identify the issues, get buy-in on proposed solutions, and implement the solutions in time for the team to execute to schedule.
Intel Silicon Photonics Product Division (SPPD) is at the forefront of silicon photonics integration. Since announcing the world's first hybrid silicon laser nearly a decade ago, our team continues to lead the industry with cutting-edge technology and efficient, scalable high-volume manufacturing. Our dedication to advanced development ensures that Intel Silicon Photonics continues to drive future data center bandwidth growth with smaller form factors and higher speeds, from 100G today to 400G and beyond tomorrow. We are looking for great talent to accelerate this journey, so if you are interested in joining our leading organization, then we want to hear from you.
In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Bachelor's degree in Electrical and Electronics Engineering with minimum of 10 years in VLSI Design with expertise in RTL-to-GDSII flow, floor planning, Clock tree synthesis and block-level/chip-level signoff
Minimum Required Qualifications:
- 6+ years of experience with all aspects of ASIC integration including floor-planning, clock and power distribution, global signal planning, I/O planning and hard IP integration
- 6+ years of experience solving SoC issues such as ESD strategies, mixed signal block integration, and package interaction.
- 6+ years of experience on integrating IP from both internal and external vendors and be willing to specify and drive IP requirements in the physical domain.
- 6+ years of experience with database management issues
- 6+ years of experience using leading-edge EDA tools Synopsys, Cadence or Mentor Graphics From a CAD tool perspective, experience with floor-planning tools, PR flows and physical design verification flows
- 6+ years of experience with TCL and Bash mastery
- Experience with hierarchical design approach, top-down design, area budgeting and physical verification convergence
- Experience in custom / data-path implementation
- Experience in integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain willing to plan, execute, course correct and optimize blocks and SoC level implementations
- Experience with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies and thermal management
- Experience with Perl and Python expertiseInside this Business Group
The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.
US, California, Folsom;US, Oregon, Hillsboro;US, Texas, Austin
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.