Mixed signal validation engineer
� Responsible for developing testbenches for and function - performance evaluation and debug of complex Mixed Signal Ips like SERDES like Ethernet, PCIe etc. Conversant in using industry standard Mixed Signal tools for the aforementioned IPs. Should be able to interpret standard specifications and architecture documents and able to communicate and work with the RTL verification teams. Conversant in understanding functionality from circuit schematics, conversant with RTL. The responsibility also includes, developing Behavioral models using RTL for the full custom and analog circuit schematics and verify the equivalence of the schematic vs the Behavioral models. Should be a team player and with good problem solving acumen.
Inside this Business Group
BTech OR MTech 4+ with years experience in high speed IO design like HSIO PCIe USB MIPI
Tools Cadence Virtuoso, XA, Verilog VHDL, Perl Phython etc.
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.