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Job ID: JR0157997
Job Category: Intern/Student
Primary Location: Santa Clara, CA US
Other Locations: Virtual US and Canada
Job Type: Intern

Graduate Intern Technical

Job Description

Graduate level intern working on next generation IO, from high-density low power inter-chip IO to high performance serial IO for servers and datacenters. Possible work includes architecture tradeoff study, timing analysis and system partition, link level signaling analysis. Responsibilities may be quite diverse and of technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school. Applicants will creatively apply the technical know-how (engineering fundamentals, scientific knowledge, systems thinking, analytical thinking, prototyping, and testing knowledge) against design constraints and boundary conditions (industrial design, cost, performance criteria and other design constraints) to research, develop and productive mass producible solutions.

The ideal candidate should exhibit the following behavioral traits:

  • Self-motivated individual willing to take and follow directions and deliver to schedule

  • Communication and interpersonal skills

  • Quantitative, analytical, and problem solving skills, problem/conflict resolution skills

  • Effective prioritization and time management skills

  • Willingness to motivate the team to deliver

  • Demonstrated Customer communications skills as internal/external customer interaction is critical for this job


Qualifications

Candidate must possess the minimum qualifications to be initially considered for this position. Relevant experience can be obtained through school work, classes and project work, internships, military training, and/ or work experience. The length of the internship is from 3 to 6 months (preferably 6 months).

This position is not eligible for Intel immigration sponsorship.


Minimum Qualifications:
Candidate must be pursuing a MS or PhD degree in Electrical Engineering, Computer Systems Engineering or Computer Science.

Minimum 6 months of experience or equivalent coursework in the following areas:

  • Knowledge of Highs-Speed Signaling. Understanding of serial link theory and operation

  • Familiarity with high-level modeling language preferred

  • Understanding of analog circuit fundamentals

Inside this Business Group

The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.



Other Locations

Virtual US and Canada



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$52,000.00-$147,000.00


Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here
Intel is committed to a culture of accessibility.  Intel provides accommodations to applicants and employees with disabilities.  Find information and request accommodation here.
USInternJR0157997
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