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Job ID: JR0170382
Job Category: Intern/Student
Primary Location: Hudson, MA US
Other Locations:
Job Type: Intern

Graduate IP Design Intern

Job Description

Intel's IP group is looking for an engineer to contribute in the high-performance power solutions IP space and grow physical design skills. We are designing innovative IP solutions across multiple technologies and unique architectures that fuels Intels' servers, clients and graphics microprocessors.

You will collaborate with architects, logic designers, and analog engineers in evaluating implementation details of complex design features. You will perform all aspects of the SoC design flow from high-level design through synthesis, place and route, timing analysis and power reduction.
You will be responsible for creating a design database that has completed sign-off flows and is ready for manufacturing.

Your responsibilities may include but not be limited to

  • IP Family and/or block-level floor planning
  • Power supply and power grid planning and analysis
  • Logic synthesis of design blocks
  • Formal Equivalence Verification (FEV)
  • Clocking network planning and analysis
  • Auto Place-and-Route (APR) using Synopsys ICC tools
  • Timing verification using Synopsys PrimeTime
  • Physical verification - Layout vs. Schematic (LVS), Design Rule Checks (DRC), Electrical Rule Checks (ERC), and Design for Manufacturability checks (DFM)
  • Reliability Verification
  • Debug and resolution of integration issues at parent level
  • Completion of design reviews and design signoff flows
  • Assist in the preparation of the full-chip layout design database for introduction to manufacturing


In addition to the qualifications listed below the ideal candidate will also have:

  • Excellent analytical and problem-solving skills
  • Strong verbal/written communication skills
  • Effective team player with continuous learning mindset
  • Willingness to balance multiple tasks
  • Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

This position is not eligible for Intel immigration sponsorship

Minimum Qualifications
Candidate must be pursuing a Masters Degree or a PhD Degree in Electrical Engineering Computer Engineering or Computer Science and:

  • Must be attending or have completed relevant coursework in digital logic or microprocessor design or computer architecture or software programming

Preferred Qualifications

  • Logic synthesis and automated place and route tools
  • Computer architecture and logic design fundamentals
  • Hardware description languages such as Verilog or System Verilog
  • Scripting skills using a programming language such as Perl, TCL, or Python

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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