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Job ID: JR0170210
Job Category: Engineering
Primary Location: Hillsboro, OR US
Other Locations:
Job Type: Experienced Hire

SOC Design Engineer - Physical Design

Job Description

Come join Intel's Client Engineering Group responsible for designing Client SoCs that make up more than half of Intel's annual revenue. We envision the future of computing and design for the next generation of laptops and desktop computers We are looking for a SoC System on Chip Physical Design Engineer ready to research design develop and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. This role is within Intel's highly regarded Devices Development Group headquartered in Portland Oregon with additional sites in Austin Texas and Penang Malaysia. Our bold purpose as a company is to create world changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology.

Your responsibilities may include but not be limited to:

  • Design planning for IP blocks including analog IP blocks partition and assembly levels of hierarchy
  • Route studies and solutions for high performance designs
  • Layout verification and signoff for IP blocks partition and assembly levels of hierarchy
  • Lead and mentor junior engineers in specific physical design domains
  • Effectively communicate with large numbers of design and layout engineers providing high quality documentation and presentations
  • Support the construction of IP blocks with external process technology providing guidance on physical integration needs to support block delivery to an external foundry
  • Drive technical activities of physical design during all phases of execution

In addition to the qualifications listed below the ideal candidate will also demonstrate the following traits:

  • Self motivator with strong problem solving skills
  • Willingness to work with teams across projects domains and geos


You must possess the below minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates

Minimum Requirements
Bachelor's or Master's degree in Electrical or Computer Engineering or a related field.
3+ years of experience in the application of methodologies and physical design for SOC and/or IP designs
2+ years of experience in 3 or more of the following specific areas:

  • Floor planning and routing
  • Physical design convergence and tape in
  • Interconnect design and analysis
  • Custom circuit layout editing Virtuoso and layout verification ICV Caliber spanning device-level through macro closure

Preferred Qualifications
4+ years of experience with semiconductor reliability physics and failure mechanisms, including electro migration EM, latch up LU, and electrostatic discharge ESD.
4+ years of experience with Ansys Redhawk or Totem.
2+ years of experience with Linux and TCLSKIL to implement automation, including familiarity with version control solutions.

Inside this Business Group

The Devices Development Group (DDG) is a global organization focused on the development and integration of SOCs, critical IPs including Atom and chipsets that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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