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Job ID: JR0170161
Job Category: Engineering
Primary Location: Phoenix, AZ US
Other Locations:
Job Type: College Grad

ASIC APR Technology Development Engineer

Job Description

About the team:

This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the DE Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems, enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams to develop and deliver high quality technology collaterals, models and enablement of EDA tools.

About the role:

As an ASIC Auto Place and Route (APR) Technology Development Engineer you will be responsible for, but not limited to the following:

  • Responsible for development of ASIC Auto Place and Route design flows and collateral using Synopsys Fusion Compiler, Cadence Innovus and Siemens Aprisa tools.
  • Perform detailed evaluation of tool run results to validate proper tool behavior and identify root cause for any discrepancies found
  • Develop and enhance automation scripts for tool regression and quality
  • Responsible for generation and quality checking of APR techfiles and other required tool collaterals
  • Develop and enhance automation scripts for collateral generation and quality
  • Develop and test Engineering Design Automation EDA tools and create flow scripts to analyze and test design methodologies
  • Responsible for designing deploying and testing efficiency of tools in achieving design goals and collaborating with design teams on methodology development
  • Candidate should be able to apply design methodologies to help execute projects effectively and successfully with high quality

This is an entry level position and compensation will be given accordingly.


The candidate must possess minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork class research and or relevant previous job and or internship experiences.

Minimum Qualifications

Bachelor’s degree or Master’s in Electrical Engineering or Computer Engineering. Must have the required degree or expect the required degree by September 2021.

3+ months experience with:

  • Programming, scripting in Unix shell, Perl, Python, Ruby or Tcl
  • Static timing analysis and synthesis
  • ASIC standard cell design using Auto Place and Route (APR)

Preferred Qualifications

  • Working knowledge of Cadence Innovus, Synopsys Fusion Compiler or Siemens Aprisa tools
  • Familiarity with semiconductor design rules and physical verification


Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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