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Job ID: JR0169622
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations: US, Arizona, Phoenix;US, California, Folsom;US, Oregon, Hillsboro;US, Texas, Austin
Job Type: Experienced Hire

PDK Application Engineer - Physical Verification

Job Description

If you have a strong technical background and like customer interaction, this is the position for you. Intel Foundry Services (IFS) Applications Engineering team is looking for independent, self-motivated candidates with strong technical skills in SOC/IP/ASIC design and methodology to work with our customers.

As part of our IFS group, you will help drive IFS technologies and solutions into customer's engineering teams as well as be the customer advocate working back with internal development teams. You will ensure Intel collaterals and services can continuously meet IFS customers' needs that would lead to successful chip tape-outs. Joining this group means you will be representing Intel enabling customers satisfying experiences and eventual outcome, financial success.  

The responsibilities for this highly visible position include: 

1. Providing ongoing support; tight collaboration with internal development teams and EDA vendors on issue resolution, preparing and delivering technical training/presentations, knocking down all barriers to successful sub-22nm customer tape-outs.

2. Drive quality design kit content and its documentation delivered to customers.

3. Promote customers use IFS Best Known Methods (BKMs).


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess at least one of the following 2 options; plus, the years of experience required for each degree in the areas specified below:

1. Bachelor's degree in Electrical Engineering, Science, Computer Science, Engineering or related field of study.

2. Master's degree in Electrical Engineering, Science, Computer Science, Engineering or related field of study.

Years of experience required per degree

6+ years (for a Bachelor's degree) or 4+ years (for a Master's degree) of experience in:

  • Development and support with industry-standard physical verification tools, Synopsys Integrated Circuit Validator (ICV) and/or Siemens (Mentor) Calibre; as applied to digital, analog and mixed-signal (AMS) designs in sub-micron CMOS technologies.

  • Programming experience in Perl, Tcl, Python, or other equivalent scripting language including but not limited to flow-related issue debug/fix, new solution/enhancement development, productivity/quality-increasing automation.

  • One of SOC design methodology, SOC integration, IP development, ASIC design or foundry design enablement/automation fields.

Preferred qualifications

  • Hands-on experience and knowledge in various types of physical verification checks (LVS, DRC, DFY/DFM, lithography) at the chip/block level or chip tape-out experience with a track record of successful signoffs.

  • Knowledge of hierarchical design approach, top-down design, budgeting, timing and physical convergence, DRC correlation with APR tool, and building Quality Assurance (QA) regression test suite a plus.

  • Experience with providing technical direction to engineering teams, including but not limited to customer support, driving methodologies and BKMs to streamline physical design work, providing specifications for guidelines and checklists, driving execution, and tracking progress while offering physical verification support.

  • Knowledge of adjacent physical design flow domains, like layout design, fill, parasitic extraction.

  • Practical experience with one of the IaaS public cloud offerings (MS Azure, Amazon AWS, Google) in semiconductor design/EDA Virtual Design Environment (VDE).

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth



Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, Oregon, Hillsboro;US, Texas, Austin



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

USExperienced HireJR0169622
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