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The applicant should have a Bachelor degree in (Electrical and Electronics or Computer or equivalent) Engineering or higher, and at least about 2 years of experience in RTL design and verification. - Familiarity or experience in RTL design with Verilog is required. - Familiarity or experience with RTL verification and timing analysis/closure is required. - Knowledge of high-speed serial system interfaces (such as PCI Express or USB) is a strong plus. - Familiarity with Perl, C++ and shell scripts is a plus. - Effective in communication, collaboration and taking initiative. - Motivated to learn and adapt to fast-evolving technologies and environments. -Graduates with no working experience but with strong academic and related final year RTL design project are encouraged to apply.
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.