In this role you will be part of Intel's Barefoot Division under the Connectivity Group working on exciting programmable switch ASIC roadmap. You will engage with Architecture, DFT and packaging to arrive at optimal chip planning early in the design cycle. You will be part of our physical design team working closely with cluster and partition leads to comprehend design challenges and arrive at optimal floorplans. You will play a critical role in die size estimation and in evaluating floorplan tools, methods and flows. Your work will involve meticulous planning of various aspects of floor planning for optimal data flow for high pin densities and to facilitate high confidence timing closure and routability. With your broad understanding of physical design you will play a critical role in identifying and solving multitude of design issues at partition/cluster and full chip.
BS in Electrical or Computer Engineering or similar degree with 4+ years of experience.
The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.
US, Arizona, Phoenix;US, North Carolina, Raleigh
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.