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Job ID: JR0169020
Job Category: Engineering
Primary Location: Folsom, CA US
Other Locations: US, Arizona, Phoenix
Job Type: Experienced Hire

Graphics Hardware Timing Signoff Methodology Engineer

Job Description

If you are passionate about computer graphics and working with leading graphics engineers on Intel's latest GPU/CPU architecture, then our Graphics & Throughput Computing Hardware Engineering (GTCHE)  team has opportunities for you. We are passionate about delivering best-in-class visual experiences for users to immerse themselves. The Visual and Machine Learning IP team is within GTCHE delivering discrete and integrated graphics IPs to client and datacenter market. In this position as a Graphics Hardware Timing Signoff Methodology Engineer you will be part a world-class IP physical design team developing groundbreaking high-performance GPU/GFX IPs that are targeted for High-End Graphics, Gaming, Artificial Intelligence, Media processing, and more. This is a great opportunity to join a talented team that is innovating in ASIC implementation and verification of multi-million gate designs in advanced process nodes across multiple foundries.

Your responsibilities may include, but not be limited to:

  • Defining and implementing signoff methodology for signoff areas of Static Timing Analysis, ERC Quality, Parasitic Extraction, Reliability Verification & Formal Equivalency Verification across internal and external foundry processes
  • Developing timing flows, understand design requirements/objectives and develop signoff conditions and milestone checklists appropriate with the design project goals
  • Collaborating with 3rd party EDA vendors to resolve issues and drive feature improvements in signoff tools
  • Working closely with process technology development team to understand process characteristics and setting appropriate design constraints to model on-chip variation effects, power-supply variation, process aging and other PV/Si miscorrelation effects in timing analysis flows
  • Engaging closely with Design teams to understand the design & convergence challenges and creating intuitive methods to provide recipes with a focus on PPA & TAT optimizations

Behavioral traits that we are looking for:

  • Good interpersonal/communication skills


Qualifications

Minimum skills and experience that will get you noticed:

This position requires a Bachelor’s Degree in Electrical/ Electronics, Computer Engineering or related discipline with 7+ years of experience. Or a Master's degree in the same field with 5+ years of experience.

Your experience should be in one or more of the following areas: 

  • Experience in ASIC Physical Design in areas of Timing analysis and convergence
  • Flow development for Static Timing analysis to meet product and process requirements
  • Proficiency with one or more of the following Industry standard EDA tools (PrimeTime, Tempus, StarRC, Genus, RedHawk, LEC/Formality or Fusion Compiler).
  • Automation skills in TCL, Perl, Shell, or Python programming for robust flow implementation
  • ASIC implementations/Signoff

Preferred skills and experience that will make you stand out:

  • Understanding of Graphics architecture, Logic Design and microarchitecture
  • Experience with circuit simulations

Inside this Business Group

Intel Architecture, Graphics, and Software (IAGS) brings Intel's technical strategy to life. We have embraced the new reality of competing at a product and solution level—not just a transistor one. We take pride in reshaping the status quo and thinking exponentially to achieve what's never been done before. We've also built a culture of continuous learning and persistent leadership that provides opportunities to practice until perfection and filter ambitious ideas into execution.



Other Locations

US, Arizona, Phoenix



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

USExperienced HireJR0169020
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