Qualifications
Design Automation Engineers are advocates of methodologies to help projects to be effectively and successfully executed with high quality In this position you will be responsible for developing and deploying custom layout design and verification flows and techniques to enable design teams in Intel Responsible for tool flow and methodology development for the design of Analog and Mixed Signal IPs on leading Intel process Responsible for development of physical verification tool flow and methodology on Intel and TSMC Process Provide Design Automation support across Business units in the toolsflows used in the layout implementation across different Intel sites Responsible for internalexternal vendor interaction developing new conceptsBKMs in the custom layout domain and deploying those capabilities to different design teams Looking for candidates with following Skill sets
Good working knowledge in Floor planning Synthesis and APR flows
Hands on expertise in using Synopsys Fusion Compiler and ICC Experience in Cadence Innovus is a plus
Good automation skills in Python PERL andor TCL andor Shell
Good communication skills written and verbal
Ability to work in a multisite team environment
Thorough understanding of Foundry PDKs and Reference Flows
The Design Engineering Group is a worldwide team responsible for the design, development, validation, and manufacturing of IPs and SOCs. Our mission is to deliver leadership products through groundbreaking innovations.
Other Locations
India, Hyderabad