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Job ID: JR0167537
Job Category: Engineering
Primary Location: Hillsboro, OR US
Other Locations: US, Arizona, Phoenix;US, California, Santa Clara
Job Type: Experienced Hire

Senior Staff Density Fill Development Engineer

Job Description

At Intel Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the Design Enablement Process Design Kit (PDK) group you will join a highly motivated team of talented engineers solving challenging technical problems enabling PDKs for Intel’s most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.

The job requires partnering and leveraging domain experts across various areas of Technology Development EDA vendors and product design teams to develop and deliver high quality technology collaterals models and enablement of EDA tools. Senior Staff Component Design Engineers in the fill development area is expected to perform the following:

  • Develop Density fill solution that meet the process requirement based on specifications
  • Work closely with Technology development on evaluating solutions software and provide feedback to ensure fill density is simplified for the customers and in line with external foundry experience
  • Strategically partner with project customers and TD to maintain density fill solution that is easy to use and does not add cycles to the designer’s timeline
  • Expected to coach junior team members and create talent inside Intel Drive EDA tool development improvements to enhance performance and functionality and improve capacity
  • Plan work and provide commitments to upper management


Minimum Qualifications:

Masters Electrical Engineering, Computer Engineering with 4+ years of semiconductor industry experience OR PhD in Electrical Engineering, Computer Engineering with 2+ years of semiconductor industry.

Experience in the following areas:

  • Density Fill runset Development using Calibre SVRF and TVF with exposure to VLSI design and execution
  • Algorithmic development and translating rules into runsets
  • TCL and Python and Unix-Linux platforms
  • Developing test cases to validate fill density runsets

Preferred qualifications:

  • Exposure to Synopsys ICV and Cadence Pegasus is a plus
  • Exposure to layout, schematic entry using Cadence Virtuoso and Synopsys Custom Designer
  • Exposure to semiconductor device physics models and technology scaling
  • Familiar with industry standard CAD tools flows for digital analog design


Inside this Business Group

Manufacturing and Product Engineering (MPE) is responsible for test development across product segments, supporting 95% of Intel's revenue. We deliver comprehensive pre-production test suites and component/physical debug capabilities to enable high quality, high volume manufacturing.

Other Locations

US, Arizona, Phoenix;US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

USExperienced HireJR0167537
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