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Job ID: JR0165943
Job Category: Engineering
Primary Location: Hillsboro, OR US
Other Locations: US, Arizona, Phoenix;US, California, Santa Clara
Job Type: College Grad

Physical Design Development and Validation Engineer

Job Description

At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.

The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams to develop and deliver high quality technology collaterals, models, and enablement of EDA tools.

As Physical Design Development or Validation Engineer, you are expected to perform the following:

  • Develop test patterns to qualify the physical design rules for correct implementations.
  • Develop automation to run regressions, auto detect issues and generate validation reports.
  • You are also expected to fil bug reports and work closely with runset developers and rule writers on validating the rules.
  • Develop Density fill solution in multiple platforms that meet the process requirement and conform to the required specifications.
  • Work closely with Technology development on evaluating density fille solutions/recipes and provide feedback to ensure fill density is kept simple for customers' ease of use and inline foundry services requirement.
  • Work with EDA on tool developments/improvements to enhance performance, add functionality and improve capacity.

This is an entry level position and compensation will be given accordingly.


You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

Master’s in Electrical Engineering, Computer Engineering or Computer Science OR PhD in Electrical Engineering, Computer Engineering or Computer Science. Must have the required degree or expect the required degree by September 2021.

6+ months experience in the following areas:

  • VLSI, circuit layout, transistor's type, and usage.
  • Algorithmic development and translating rules into runsets
  • TCL, Python and Unix-Linux platforms.

Preferred Qualifications:

  • Exposure to Calibre SVRF and TVF, Synopsys ICV and cadence Pegasus is a plus.
  • Exposure to layout and/or schematic entry using Cadence Virtuoso and/or Synopsys Custom Designer
  • Exposure to semiconductor device physics models and technology scaling


Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth

Other Locations

US, Arizona, Phoenix;US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

USCollege GradJR0165943
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