IP Logic Design Engineers are responsible for the design and development of various protocols and buffering systems in the network interface cards. Responsibilities may include the protocol analysis for the best throughput and latency metrics, microarchitecture, RTL design, & timing closure. Require the ability to document the microarchitecture and design in terms of the pipelines, FSMs and logic diagrams. Need to plan the timelines of the deliverables and deliver them on time and with quality. Adept at ASIC design methodologies and the respective tools (such as Lint, CDC, RDC). Support of the designers is expected in the debug activities, during pre-Silicon and post-Silicon validation and emulation.
Senior designers are expected to lead the innovation through patents and publications that demonstrate the product success. Respond to customer client requests or events as they occur, developing solutions to problems utilizing formal education and judgement. Mentor the junior designers, as applicable. Proven experience in the networking protocols (Ethernet, IP v4/6, TCP/UDP), bus protocols such as AMBA and/or PCIe; is desired.
BSc in Electrical or Computers engineering 6 years of relevant experience in chip design with familiarity with the entire development flow from definition to Tape Out. Good problem solving ability, Excellent communication skills are desired. Networking protocols knowledge is an advantageInside this Business Group
The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.