Develops preSilicon functional validation tests to verify system will meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing.
Bachelor in Engineering with 12+ years of experience in IP/SS/SOC pre-Si validation with in-depth expertise in System Verilog and UVM concepts.
As a senior val engineer, you should be able to independently develop and drive pre-Si validation for varied IP, sub-system, SOC level validation. Create test plan, build test bench architecture and come-up with test methodology. Create and own schedules.
Should be able to provide technical leadership and direction to junior val engineers in the group and able to come up with technical proposals helping implementation.
Assist Pre-Silicon Verification team in developing Test plan and test coverage. Review the coverage reports from regression tests and provide feedback to design/verification team.
Collaborate with Architecture, design, SOC validation, system validation and Firmware/software teams for platform level debug.
Participates in the development of Architecture specifications for the Logic/Val components. Provides IP integration support to SoC customers and represents Val team.
Excellent communication and interpersonal skills are critical.
Experience in High speed serial protocol is added advantage.
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.