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Job ID: JR0154526
Job Category: Engineering
Primary Location: Folsom, CA US
Other Locations: US, Arizona, Phoenix;US, California, Santa Clara;US, Oregon, Hillsboro
Job Type: Experienced Hire

Design Automation Engineer

Job Description

About the team:

The position offered is for a Design Automation Engineer in the Design Rule Optimization (DRO) team of the Process Design Kit (PDK) group, within the Design Enablement (DE) organization. A key function of the DRO team is to further develop and deploy software to formally model and streamline delivery of machine-readable design rule data to PDK development teams, allowing them to employ automated techniques in collateral and layout test case generation.  Additionally, the DRO team works closely in partnership with Intel’s advanced process technology definition team, EDA suppliers, and PDK developers to optimize Intel's process technology competitiveness using traditional automation and Machine Learning (ML) techniques.

About the role:

  • Develops and tests Engineering Design Automation tools, creates flows/scripts to analyze and test design methodologies.
  • Writes automation to automatically create highly permuted layout test cases to assess process technology competitiveness.
  • Evaluates vendor practical capabilities to provide required products or services.
  • Responsible for designing, deploying and testing efficiency of tools to utilize in achieving design goals and collaborating with design teams on methodology development.
  • Design Automation Engineers are advocates of applying design methodologies to help execute projects effectively and successfully with high quality.

Behavior traits we look for:

  • Behavioral history with respect to quality
  • Customer orientation
  • Problem-solving skills


Qualifications

Minimum qualifications:

Possess a Bachelors in EE/CS/CE with 6+ years of industry experience or Masters in EE/CS/CE with 4+ years of industry experience.

Industry experience the following areas:

  • Custom layout experience within a DA role involving backend EDA tools (layout editors, tech files, Pcells, auto-routing, macros, environment, etc.) and design rule familiarity on advanced process nodes.
  • Understanding of layout design rule concepts, on advanced process nodes.
  • Programming languages such as C++, Python, Ruby, or Tcl as well as experience in using the UNIX/Linux operating system is a requirement.

Preferred:

  • Development and support of build processes using a continuous integration system and/or Makefile-type of build flow.
  • Problem-solving to model design rule concepts into formal EDA tool constraints/rules.

#designenablement

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth



Other Locations

US, Arizona, Phoenix;US, California, Santa Clara;US, Oregon, Hillsboro



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

USExperienced HireJR0154526
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