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Job ID: JR0148871
Job Category: Engineering
Primary Location: Hillsboro, OR US
Other Locations: US, California, Santa Clara;US, Massachusetts, Hudson
Job Type: Experienced Hire

Analog Design Engineer

Job Description

Intel's IP Engineering Group (IPG) is looking for Senior/Staff Design Engineer to play a critical role in the power delivery and Voltage Regulator space for Intel's flagship client/server/graphics/FPGA/networking SOC designs.

Responsibilities include:

  • Analog micro-architecture, technology pathfinding, specification, IC circuit design, layout supervision, documentation, DFT and DFM of analog and mixed signal clock generation units, leading and mentoring of team members and active collaboration with colleagues and partners across different design disciplines. Minimal travel may be required.

Analog design responsibilities may consist but not limited to:

  • High performance, high efficiency on-die Voltage Regulator, Bandgap References, low jitter PLL, high speed analog to digital and digital to analog converters, custom power supply networks and other elements necessary to design, verify and productize high performance analog and mixed signal Power Delivery IP solutions.

In addition to the qualifications listed below, the ideal candidate will also have:

  • Excellent verbal and written communication skills
  • Strong teamwork skills and the willingness of performing in a dynamic work environment
  • Willingness to be flexible between multiple roles throughout the life of the project


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

The candidate must have a Bachelor's degree in Electrical/Computer Engineering and 8+ years of experience -OR- Master's degree in Electrical/Computer Engineering and 6+ years of experience -OR- a PhD in Electrical/Computer Engineering and 4+ years of experience in:

  • CMOS Analog or mixed-signal circuit design (Amplifiers, LDOs, PLLs, ADCs, ...)
  • Layout methods in advanced process nodes for analog circuits (optimization for parasitics, matching,...)

Preferred Qualifications

1+ years of experience with:

  • Knowledge of Power Delivery / Power Management systems

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Santa Clara;US, Massachusetts, Hudson

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

USExperienced HireJR0148871
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