IP Front End Design Manager

At Intel, we work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver IP solutions for products that impact customers lives?

Intel's Analog and Mixed Signal IP Group(AMSG) is looking for an experienced Design Manager to contribute in the high performance delivery/Voltage Regulator/Low Drop Out/Bandgap IP space for Intel's flagship client/server/chipset/Graphics SOC designs. This is a hands on first level management position in which you will have the opportunity to manage, grow and provide mentoring to a large design team of talented logic and Verification engineers. You and your group's responsibilities will include but not be limited to:

• Partnering with architect, logic and Verification technical leads and delivering high quality front end design and documentation to SOC/SOP customers on schedule
• Schedule and track pre-silicon Logic and VAL development, manage and track post silicon activities
• Working closely with cross site disciplines such as physical design, analog, design automation, sub-IP/collateral providers
• Plan and support IP integration support to SOC customers in both pre-silicon and post silicon cycle
• Partnering with Tool Flow Methodology team
• Managing and growing the team with strong track record and expertise
• Cultivating and reinforcing appropriate group values, norms and behaviors
• Identifying and analyzing problems, plans, tasks, and solutions
• Providing guidance on employee development, performance, and productivity issues.

The ideal candidate should exhibit behavioral traits such as:

• Excellent written and verbal communication skills, self-motivation, proactiveness.
• As part of a growing, dynamic team, the candidate should have maturity to manage the team under challenging execution situations with hanging requirements, in an innovative environment.

Qualifications

Minimum Qualifications:

The successful candidate will possess a Bachelor's Degree in Electrical Engineering or Computer Engineering with 6+ years of combined design and management experience - OR- a Master's Degree in Electrical Engineering or Computer Engineering with 4+ years of combined design and management experience -OR- a PhD degree in Electrical Engineering or Computer Engineering with 2+ years of combined design and management experience in:

• IP or SOC development

Candidate will also have experience with the following skills:

• Mixed signal design or validation,
• Logic design using System Verilog
• Micro-architecture trade-offs and documentation
• Low-power design using UPF and clock gating
• Multiple clock domain design
• IOSF Sideband and Chassis
• State machine design
• TAP Controller and DFX
• Simulation and debug experience using VCS/Verdi
• Customer support and debugs for SOCs
• Synthesis and speed path debug
• Standard IP/SOC Design tools and methodologies

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.