Come and join our task force, you will be responsible for design methodologies and CAD support of digital blocks from complex AMS IPs like HSIO, DDR- Ethernets- PLL, etc.
Key responsibilities include but are not limited to
- Physical Design logic signoff in STA and Low Power on advanced process nodes 10nm and below.
- Work closely with Design teams to understand the design and convergence challenges plus derive methods to provide recipes with a focus on PPA and Turnaround time optimizations.
- Work with internal IP design implementation teams on tactical implementation and design closure aspects and enable design teams in all aspects of Physical Design OR Timing Signoff wrt Tools Flows and Methods.
- Understand project schedules and foresee design team requirements. Extensive communication required with customers in multi-geographic regions.
- Work with 3rd party EDA vendors and internal IP teams to resolve issues and drive improvements in vendor tools design convergence and signoff.
The Product Enablement Solutions Group (PESG) is a worldwide organization that delivers an end-to-end design system for development of IPs, Cores and SOCs. This business group partners with the Semiconductor, IP and EDA eco-systems and leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to deliver a world-class design system that powers Intel’s leadership products.