Design and development of mixed-signal circuits such as High Speed TX and RX, Various type of compensation circuitry, equalizers, DLL, clocking circuitry such as duty cycle detection/correction, on die voltage regulators, DAC, ADC, Voltage references, power gates, power good, high speed level shifter, ESD/Clamps and View observation circuitry.
- Own design verification plans covering functional, performance and reliability meeting high volume manufacturing requirement.
- Participate in circuit design review, preparing circuit constraint through CCM as guideline for Mask Designers on layout implementation and floorplan review, reliability results review and audit with QRE.
- Responsible on collateral generation such as Integration Guide, Timing model, Noise model, RTL/BMOD model, Power data, IBIS model, ICCT profile, RV report on circuits being owned and ensuring quality through central QA run which ensure consistency across all collaterals being generated before handoff to another team.
- Collaborate with FE Logic designer on integration of Analog Circuit CBB into PHY level particularly in BMOD coding, FEV, SCAM and MSV validation.
- Collaborate with BE Structural Design PV engineer on Analog Circuit timing model being generated to meet timing closure requirement at PHY level.
- Collaborate with Platform Signal Integrity and Power Delivery team that using generated IBIS & ICCT model for optimum platform solution.
Experience in the Design of high-speed analog and mixed-signal design for DDR4/LP4/DDR5/LP5 DDR PHYs with involvement definition to productization on at least 2 full projects.
- Good understanding of design for yield and exposure to production challenges in latest technology process node. Prefer design knowledge of 20nm and below.
- Experience with industry standard tools for Analog design such as Cadence ADE, Spectre, AMS verification, FEV, StarRC etc.
- Cross-discipline knowledge in any of these areas, such as Analog integration, RTL/System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid, Memory IO training MRC and HAS/MAS specification documentation.
- Strong written and oral communication skills.
- Positive attitude and team player.
- BSEE with 7+ years relevant experience or Master's with 5+ years relevant experience required. Education Focus should include integrated circuit design and analog design.Inside this Business Group
Intel Architecture, Graphics, and Software (IAGS) brings Intel's technical strategy to life. We have embraced the new reality of competing at a product and solution level—not just a transistor one. We take pride in reshaping the status quo and thinking exponentially to achieve what's never been done before. We've also built a culture of continuous learning and persistent leadership that provides opportunities to practice until perfection and filter ambitious ideas into execution.