Performs logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs.
Participates in the development of Architecture and Microarchitecture specifications for the Logic components.
Provides IP integration support to SoC customers and represents RTL team.
As a DDR PHY engineer, you will be involved with all phases of PHY design of high-performance GDDR/HBM and chip-to-chip interconnect; from architecture, RTL to delivery of final GDS. You will participate in early product definition of next-gen IO solution, micro-architecture development, define testing, physical integration and verification strategy, identify timing bottlenecks and work closely with CAD and PD teams to address it. You will champion development of the best-in-class designs maximizing the Performance/Watt.
Responsibilities:
Drive best in class RTL and Validation design methodologies
Define & refine front-end development methodologies for PSG and IP development organizations
Advance front-end design methodologies for SoC applications - reduce the amount of duplication (design and validation) work by SoC teams
Work with the development team to implement the front-end solutions
Oversee definition, design, verification, and documentation for High Speed Parallel IO Designs.
Determine architecture, logic design, system validation, training (firmware) and characterization requirements. Include DFT, DFX, Power intent, Signal Integrity and functional coverage analysis.
Drive memory training and calibration (continuous) algorithms and hardware/circuits required for this.
Define module interfaces/formats for physical integration and functional validation. Work closely with peers in layout, structured design, validation, emulation, FPGA software and product characterization groups.
Automate design tasks to complete the design in the most efficient approach. Champion productivity improvement metrics within the hardware organization.
Familiar with all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
Self-motivator with a penchant for solving problems at the cutting edge of technology
Strong leadership skills with ability to mentor junior designers. Excellent interpersonal skills, including written and verbal communication
Qualifications
B.Tech ( EE ) with 15+ years relevant experience or Master's with 10+ years relevant experience required.
- Strong written and oral communication skills
Inside this Business GroupIntel Architecture, Graphics, and Software (IAGS) brings Intel's technical strategy to life. We have embraced the new reality of competing at a product and solution level—not just a transistor one. We take pride in reshaping the status quo and thinking exponentially to achieve what's never been done before. We've also built a culture of continuous learning and persistent leadership that provides opportunities to practice until perfection and filter ambitious ideas into execution.
