Develops and supports design for test (DFT) structures.
Determines design for test approaches and develops DFT architecture. Designs and verifies DFT structures for memories (MBIST), digital and analog circuitry. Performs scan synthesis.
Creates, simulates and verifies automatic generated test patterns (ATPG). Creates functional tests and corresponding test patterns. Knows about failure mechanisms in silicon production and creates test algorithms.
Supports silicon bring up of test patterns. Performs diagnosis of test patterns on silicon and optimizes test time.
o BSc. in Electrical Engineering with 2+ years of applicable experience.
o Experience in Verilog including behavior model construction and verification.
o Familiar with scripting language like Perl/Python/Tcl in Unix environment.
o Experience in SCAN ATPG or Memory BIST is highly desired.
o Experience in post silicon debug and bring-up on the ATE - an advantage.
o Self-Starter with strong multitasking skills.
o Good interpersonal communication skills with an ability to work in a team
o Quick learner, proactive and self-motivated, eager to learn and contribute.
o A sense of ownership, commitment, and responsibility