As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
- Your responsibility will also include verification and silicon bring up of Scan ATPG and other DFT features.
- In addition, you will help develop and deploy DFT methodologies for our next generation products.
- Working with soc/post silicon team to improve/ address low scan coverage and implement methodology to enhance scan coverage is expectation.
- Collaborate with the RTL designers and other Verification Engineers to find creative ways to accelerate the identification of functional defects.
Candidate should possess a Bachelor/Master degree in VLSI/ Electronics with 7-12 years' experience in the below mentioned skills.
Inside this Business Group
- Experience in various aspects of DFT - SCAN insertion, ATPG, MBIST & JTAG, BSCAN. Test generation, coverage improvement, post-silicon debug.
- Well verse with OVM/UVM validation methodology on building Test bench to implement monitors, checkers, scoreboard.
- Hands on experience on DFT industry standard tools from Cadence, Mentor Graphics used for SCAN insertion, MBIST implementation and validation is must have requirement.