ESIP department (Ethernet and SerDes IP’s) is looking for an Analog Engineer experienced in analog design for integrated circuits.
ESIP develops and delivers High Speed networking and communication IPs (such as Ethernet PHY, PCIE, USB-TypeC, DP/HDMI) to all Intel devices (Client and Servers CPU’s / Chipset / Controllers).
Team delivers state of the art analog PHYs (receivers and transmitters) circuits for the most advanced standards like 112Gb/s and higher Ethernet PHY in Intel/TSMC process (14nm/10nm/7nm/5nm).
As part of your role, you will participate in next client and Ethernet advanced PHY analog blocks design like ADC, VGA, CTLE, DAC, PLL, TX targeted to Data-centers and SOC next generations.
You are equipped with all analog design skill sets of architecture and research, modelling, design and simulation, validation and silicon testing.
You have proven background in academia and industry as well as excellent human relations skills.
BSc, MSc or PhD in Electrical Engineering or Computer Engineering, specializing in analog circuits or communication
At least 5 years of experience in analog chip design.
Creativity and team work
Knowledge in PHY design and high speed analog circuits is advantage.
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.