Experience in validation/verification at IP and/or SOC level.
Experience with System Verilog/OVM/UVM development environment is must with experience on coverage
Experience in post silicon debugging
Exposure to cache coherency, I/O protocol, accelerator will be an added advantage
Experience in tracing rtl code for the purpose of debugging post si failure
Knowledge of cache coherency protocol
Knowledge of Clocking, Boot/Reset flows.
Demonstrate excellent Self-motivation, communication, strong problem solving and teamwork skills.
Set aggressive goals and meet/beat the commitments.
Flexible enough to work in a dynamic environment and multitask seamlessly.
Ability to work independently and in a team.
Bachelor's degree or Master's degree with 7-12 years of experience in VLSI, Electronics, Electrical, Computer Engineering or Computer Science.Inside this Business Group
The Design Engineering Group is a worldwide team responsible for the design, development, validation, and manufacturing of IPs and SOCs. Our mission is to deliver leadership products through groundbreaking innovations.