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Job ID: JR0153407
Job Category: Engineering Support
Primary Location: Toronto, ON CA
Other Locations: US, California, Santa Clara;US, Oregon, Hillsboro;US, Texas, Austin
Job Type: Experienced Hire

Power Integrity Architect

Job Description
Are you passionate about compute and graphics and disrupting the industry with your innovations? Working with leading engineers on Intel's latest GPU/XPU/CPU architecture? Do you love collaborating with diverse teams to help achieve best-in-class visual experiences that enable users to immerse themselves in a new visual future? If you answered yes to any of these questions, then our Product Architecture Engineering (PAE) Team has opportunities for you. In PAE we deliver Intel's integrated and discrete GPUs, which include 3D graphics, multimedia/video, 4K+ display, and parallel computing technologies. Our Team is a key element in driving Intel's entry into market segments served by high performance discrete graphics processors and hardware. Participation in market segments served by discrete graphics requires the delivery of reference platforms to downstream customers with sufficient confidence in the design to ramp this design or very close derivative into high volume production quickly, and our dGPU Platform System Engineering team is responsible for the delivery of these platforms. The Discrete Graphics Platform System Engineering team is looking for a talented Power Integrity Architect to join our team developing leading edge discrete GPU system solutions for the desktop, mobile and server market. Your responsibilities will include, but are not limited to: � Developing SOC, package, platform and system power delivery and routing strategy including guidelines. � Modeling end to end package, board, connector, etc., including electrical workloads and performing power integrity simulation for various IPs, interfaces and voltages � Defining and evaluating circuit design features required to support performance requirements and platform constraints. � Understanding how complex workloads impact power integrity � Architecting mitigation technics for minimizing these impacts � Creating Power integrity measurement and test plans and review of measurement results. � Correlating measurements to simulations, and modifying models as required � Working with cross-functional teams and engaging with Silicon Architects, Power Architects, Platform architects, Package Designers, and external customer support teams, etc.


BS/MS/PhD in Physics, Electrical/Computer Engineering, or related fields plus Minimum 10+ years of professional experience in a semiconductor industry, in a research and development environment Your experience should be in the following: � Experience with Power integrity and Power Delivery analysis � Experience in Control loop theory end to end from voltage regulator to the load � Experience with lab equipment for high-speed digital and analog systems � Experience with correlating simulation/silicon results. � Experience with the following tools and flows: Hspice, Sigrity (Power SI), ANSYS (HFSS, SIwave), SiMetrix, MathCad, MathLab, ADS � Experience in multi-stage DC-DC � Strong understanding of Electromagnetic fundamentals and transmission line theory Understanding of jitter and how it impacts the design in the system environment and Able to navigate in layout tools used for PCB and Packages High speed channel simulations for low BER and transient simulation for SI and PI, Multi-chip package design Familiarity with IC design flows, floor-planning, IO ring design, on-chip decoupling � Understanding of power management and flow between HW, FW and SW interactions

Inside this Business Group

Intel Architecture, Graphics, and Software (IAGS) brings Intel's technical strategy to life. We have embraced the new reality of competing at a product and solution level—not just a transistor one. We take pride in reshaping the status quo and thinking exponentially to achieve what's never been done before. We've also built a culture of continuous learning and persistent leadership that provides opportunities to practice until perfection and filter ambitious ideas into execution.

Other Locations

US, California, Santa Clara;US, Oregon, Hillsboro;US, Texas, Austin

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....

Intel is committed to a culture of accessibility.  Intel provides accommodations to applicants and employees with disabilities.  Find information and request accommodation here.

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