The engineer is responsible for the physical design of high density package substrates for Intel GPUs. The engineer must have a good understanding of flip chip interconnect based leading edge substrate design rules and package assembly driven constraints and rules. The role requires the engineer to collaborate and work with multiple stakeholders spread across different geos, in a fast-paced environment, from pathfinding phase to the package substrate tape out.
Must have experience of at least delivering 2 high density flip chip interconnect based package designs, with engagement from planning/pathfinding phase. The design engineer must have a strong understanding of the complete Package design flow related to flip chip designs.
The responsibilities include:
- Working with Full chip/IP development teams to drive and plan optimal bump patterns, meeting the electrical/performance requirements, substrate and assembly design rules, and cost targets. This requires to lead the design efforts and develop multiple design options swiftly in a dynamic cross-functional environment during the design cycle.
- Leading the package design efforts for the development of pin map/ball map, in collaboration with the System Hardware, Power Integrity, and Signal Integrity engineers.
- Driving the substrate physical design reviews as per plan, and meet the schedule and quality expectations.
- Validating the design using design validation tools.
- Ensuring timely release/tape out of cost optimal high quality package substrates, after reviews with internal stakeholders and with the package substrate manufacturing vendors.
- Identifying areas for improvement - for ex: design tool features, design efficiency, design methods, and proactively seeking to partner with experts/teammates to drive the improvements.
- Providing inputs to the substrate and package assembly technology development teams to enable development of industry-leading designs.
- 2-5 years of experience in the development of competitive Packages for high speed products like CPUs/ASICs/Chipsets/GPUs.
- Strong understanding of package substrate design and package assembly rules.
- Must have solid experience in designing packages with Mentor Graphics (Expedition)
- Exposure to different Package technologies, an advantage.
- Proven stakeholder management skills, in a global set-up, with technical teams spread across different geos.
- Master's in Electrical Engg with 2+ years experience or Bachelor's with 5+ years experience.
The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.