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Job ID: JR0123537
Job Category: Engineering
Primary Location: Munich, DE
Other Locations:
Job Type: Experienced Hire

Senior Expert Digital and Mixed-Signal Implementation and Signoff Methodology m/f/d

Job Description

As the expert in the Digital Design Implementation Methodology (RTL to GDSII) you will work with highly skilled engineers to develop and support highly competitive SoC methodology and flow solutions in leading edge technology nodes. You will develop provide and support methodologies to our customers for outstanding products. To succeed in this highly competitive environment we are looking for an expert in a culture of high performance, agility, flexibility and nimbleness.

Your major accountabilities cover tasks in the area of Place & Route, UPF based power methodology with focus on timing closure for digital and mixed-signal products:

  • Work closely with Intel's product teams to understand their requirements from a technical and schedule/business perspective
  • Plan and execute methodology projects to provide and support best in class methods
  • Drive innovation concerning extraction/timing methodology to address productivity, best power performance and area (PPA)
  • Prepare and present reports outlining the outcome of technical projects and make recommendations for actions necessary to achieve desired results.


Internal and External Interactions

  • Including Project Customers and Vendor Interactions
  • Author and provide continual on-the-job training for customers
  • Work as part of cross-geo international team and actively participate, contribute and drive towards best methodology and flow
  • Exposure to Intel and industry leading process technology capabilities


Qualifications

The suited candidate has substantial experience in SoC development or in related design automation engineering functions, with, ideally, experiences in working in product teams and leading teams.
Skills should include:

  • Expert in digital design and implementation of complex SoCs using advanced technology nodes (16nm and below)
  • Timing analysis and signoff for complex digital designs
  • Project management skills
  • Strong interpersonal and very good verbal/written communication skills
  • Role model collaboration across geographies and organizations

Education

  • Degree in Physics, Electrical Engineering or Computer Science
  • PhD/MS or BS with 5+ years of relevant experience

Keywords
Design Automation, EDA, RTL2GDS, Synthesis, Place and Route, Static Timing analysis, Synopsys, Cadence, ICC2, PT, Innovus, Tempus, Foundry

Inside this Business Group

The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.

DEExperienced HireJR0123537
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