As the expert in the Digital Design Implementation Methodology (RTL to GDSII) you will work with highly skilled engineers to develop and support highly competitive SoC methodology and flow solutions in leading edge technology nodes. You will develop provide and support methodologies to our customers for outstanding products. To succeed in this highly competitive environment we are looking for an expert in a culture of high performance, agility, flexibility and nimbleness.
Your major accountabilities cover tasks in the area of Place & Route, UPF based power methodology with focus on timing closure for digital and mixed-signal products:
Internal and External Interactions
The suited candidate has substantial experience in SoC development or in related design automation engineering functions, with, ideally, experiences in working in product teams and leading teams.
Skills should include:
Design Automation, EDA, RTL2GDS, Synthesis, Place and Route, Static Timing analysis, Synopsys, Cadence, ICC2, PT, Innovus, Tempus, Foundry
The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.