Inside this Business Group
Design Automation Engineers are advocates of methodologies to help projects to be effectively and successfully executed with high quality. In this position, you will be responsible for developing and deploying custom layout design & verification flows and techniques to enable design teams in Intel. Responsible for tool, flow & methodology development for the design of Analog & custom digital designs on leading Intel process Responsible for development of physical verification tool, flow and methodology on Intel Process
Provide Design Automation support across Business units in the tools/flows used in the layout implementation across different Intel sites. Responsible for internal/external vendor interaction, developing new concepts/BKMs in the custom layout domain and deploying those capabilities to different design teams.
Your responsibilities will include but not be limited to
- Expertise in Custom Layout Tools and AMS flows like Virtuoso.
- Experience in design and debug custom layouts
- Good working knowledge in APR flows
- Good understanding of chip finishing and DFM flows
- Good automation skills in SKILL, PERL and/or TCL and/or Shell*
- Good communication skills (written and verbal)
- Ability to work in a multisite team environment
-Thorough understanding of Foundry PDKs and Reference Flows ( TSMC/UMC)
The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.