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Job ID: JR0122825
Job Category: Engineering
Primary Location: Hillsboro, OR US
Other Locations: US, Arizona, Phoenix
Job Type: College Grad

Physical Design Engineer

Job Description

Creates bottomsup elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, fullchip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires extensive knowledge and practical application of methodologies and physical design.

This is an entry level position and compensation will be given accordingly


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications

  • Bachelor’s degree in Electrical Engineering or Computer Engineering with VLSI design and software development skills.
  • Minimum of 6 months of experience in CMOS layout design.
  • Minimum of 6 months of experience in software development.

Preferred Qualifications

  • Experience with software development/programming languages (e.g. C/C++, Perl, Python, SKILL, Ruby, TCL)
  • Ability to solve complex problems using efficient computer algorithm and effective programming techniques.
  • Experience working on with UNIX/Linux computer platforms.
  • Experience in VLSI circuit, CMOS layout design and understanding of layout design rules.
  • Exposure with industry standard integrated circuits (IC) design CAD tools/flows.
  • Specific experience with CAD tools like Cadence Virtuoso, Synopsys IC Validator or Mentor Calibre is preferred.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth



Other Locations

US, Arizona, Phoenix



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....

USCollege GradJR0122825
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