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Job ID: JR0122660
Job Category: Engineering
Primary Location: San Jose, CA US
Other Locations: US, Oregon, Hillsboro
Job Type: Experienced Hire

FPGA and ASIC process definition and DTCO technologist

Job Description

As a FPGA and ASIC process definition and design-technology co-optimization (DTCO) technologist, you will lead the definition and optimization of process technology and design implementation to enable programmable and custom products which provide a competitive advantage.

Responsibilities include, but are not limited to:

  • Lead the definition of process requirements and metrics for FPGA and ASIC products, evaluation of process and design implementation options to provide competitive advantage, engagement with process technology and design enablement teams to close PPA gaps, and co-optimization of process/collateral/design/architecture to achieve technology entitlement
  • Explore opportunities for product performance/power/area improvement through transistor selection, transistor landing zones, interconnect stack definition, design rules, cell library definition, design implementation methodologies and other process/design optimizations
  • Creation and maintenance of benchmark circuits and test cases used to predict performance and power of key FPGA and ASIC blocks including programmable fabric/routing, place-and-route blocks, memory and analog/IO circuits
  • Development and implementation of methodologies to quantify performance, power and area scaling expected for products developed on new technology nodes including both internal processes and external foundry processes
  • Support technology definition/optimization and impact evaluation of device and interconnect process changes using benchmark circuit simulations
  • Support development of layout best practices and definition of design rules/templates to achieve optimum results for FPGA and ASIC performance/power
  • Collaborate with hardware design team on development and definition of circuit simulation and timing analysis methodologies to achieve full process entitlement for performance, power and yield with minimal guardband
  • Collaborate with hardware design team on development and implementation of methodologies to minimize gap between pre-layout predictive simulations and post-layout results
  • Collaborate with hardware design team and model development team on definition and implementation of compact model capabilities required to implement product design with quality, accuracy and efficiency
  • Develop and implement methodologies for QA, evaluation and documentation of new compact model releases


Qualifications

Minimum Requirements:

  • MS or Ph.D. in Electrical Engineering
  • 5+ years of experience in a process definition or design-technology co-optimization role
  • 5+ years of experience with one or more of the following: Circuit design, CMOS device physics, process integration, compact modeling, circuit simulation, benchmark circuit development and analysis, timing analysis

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, Oregon, Hillsboro



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....

USExperienced HireJR0122660
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