Test Chip Design Engineer analog
In a world where the structures on chips are moving towards physical limitations and new devices are being invented and scaled (e.g. FinFET), early Silicon verification of product & platform relevant critical IP/FIP/tech KPIs becomes becomes more and more crucial.
This is a position at Technology Enablement Group in Bangalore, joining a team of experienced engineers working on different fields of technology enablement like process design kit development (PDK), library development and integration, test structure design, product support and design automation.
As analog full-custom test chip design engineer you will be responsible for design, layout & verification of advanced structures and circuits in most modern FINFET technologies for early Si-verification of IP / Foundational IP and key performance indicators.
On top you would be responsible for an early implicit pipe-cleaning of the design flow (pre-alpha-user).
In this position in an intercontinental team and project set-up continuous learning as well as professional communication skills are mandatory as you will be confronted with many new challenges during your daily work
Inside this Business Group
- Degree(BS/MS) in electrical/electronics engineering, physics, material sciences, software engineering or equivalent
- 5-10 years of experience in analog/mixed signal design and the related EDA tools are required
o Cadence Virtuoso for layout generation
o verification with Mentor Calibre DRC/LVS, SNPS ICV; ERC;
o Schematic generation and verification
o Design / layout extraction with QRC
o Simulation (SPICE)
o Skill scripting
o CDL netlist understanding
- Experience with Windows, Office tools and UNIX/LINUX systems required.
- Good communication skills needed
The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.