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Job ID: JR0122529
Job Category: Engineering
Primary Location: San Jose, CA US
Other Locations: US, Texas, Austin
Job Type: Experienced Hire

P&R Automation Engineer

Job Description

Our Design Automation team supports world class FPGA product design teams. We are looking for an energetic P&R (Place and Route) automation engineer to work with project P&R teams to resolve flow related issues promptly to keep project development moving forward steadily. The engineer will setup experiments to isolate issues reported by the project team and then test candidate solutions. They will track outstanding issues with the internal vendor support team as well as the vendor directly when appropriate. As a flow developer, they will customize the P&R flow for the project needs and release the P&R flow as a standardized resource to the project team in regular updates.

This engineer will be able to guide project P&R engineers in the use of best practices for performance, power, area, and schedule optimization. In the event that a project team member is stuck, the engineer will leverage ICC tool expertise to unblock the situation and move forward toward the project goals. As our flows utilize industry standard tools, it is preferred for the individual to have EDA industry experience to understand the general operating procedures of vendor companies in the resolution of issues.

As this team position will support the most challenging technical problems, the engineer must have a mindset of continual learning to stay current with the state of the art in P&R industry practices. Towards this goal, the individual should be self-motivated, a fast learner, and able to communicate learnings clearly to a wide audience. The right person will feel personal reward from helping others to succeed.


Minimum Qualifications:

  • 5+ years total experience in physical design implementation
  • 2+ years hands on experience using ICC (IC Compiler from Synopsys) for the implementation of area, frequency, and power constrained designs
    • Experience debugging ICC results to determine why area, frequency, and power issues have occurred
    • Capability to implement ICC build recipes and analysis using Tcl scripting within the tool
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Preferred Qualifications:

  • Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science
  • 1+ year experience debugging LVS/DRC issues
  • 1+ year experience debugging PT-SI timing issues
  • 1+ year experience using Cadence LEC or Synopsys Formality to debug logical equivalence mismatches

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US, Texas, Austin

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....

USExperienced HireJR0122529
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