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Job ID: JR0122365
Job Category: Engineering
Primary Location: Bangalore, KA IN
Other Locations:
Job Type: College Grad

Product Development Engineer

Job Description
Responsible for ensuring the testability and manufacturability of integrated circuits from the component feasibility stage through production ramp. Make significant contributions to design, development and validation of testability circuits. Evaluation, development and debug of complex test methods. Develops and debugs complex software programs to convert design validation vectors and drive complex test equipment. Creates and tests validation and production test hardware solutions. Tests, validates, modifies and redesigns circuits to guarantee component margin to specification. Analyzes and evaluates component specification versus performance to ensure optimal match of component requirements with production equipment capability with specific emphasis on yield analysis and bin split capability. Analyzes early customer returns with emphasis on driving test hole closure activities. Creates and applies concepts for optimizing component production relative to both quality and cost constraints. Autonomously plans and schedules own daily tasks, develops solutions to problems utilizing formal education and judgment.


Qualifications

Job Description:
In this position, you will be responsible for
? Test vector/content implementation and validation of various DFT features such as Scan, MBIST, JTAG, BScan, etc. for Intel's leading edge SoC designs.
? Working with pre-Si design/DFT teams to provide feedback and ensuring vectors are meeting ATE requirements
? Stabilizing vectors/content from Si bring up to volume production, meet DPM requirements and test cost requirements
? Delivering best in class product impacting Intel's bottom line.
? Proven Experience in Design for Test/Debug logic design/implementation of Large SOCs
? Expertise in analog DFT & in depth knowledge in mixed signal IP test
? Expertise in Scan, ATPG, at-speed test, memory test, algorithms, Boundary scan & JTAG.
? Good experience in micro-architecture, RTL coding, system Verilog, test bench development Knowledge of other ad-hoc DFT tests, on chip inter connect buses
? Experience with Synopsys and/or mentor tools and basic understanding of the SoC development flow is must
? Expertise in Si debug, shmoo analysis, statistical analysis to meet DPM and Test Cost targets.
? Knowledge of scripting in Perl, shell, etc.

Qualification:
? Candidate should possess a Bachelors or Master's degree in Computer/ Electrical/Electronic Engineering with about 4-8 years of experience.
? Strong knowledge of DFT architecture, design, methodologies and tools - Scan, MBIST, Analog DFT, JTAG, etc. Good understanding of Test Engineering & tester debug is desirable.
? Hands on design/validation experience with strong/proven debug skills.
? A very good team player with good interpersonal, planning and communication skills.

Inside this Business Group

The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.

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