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Job ID: JR0121899
Job Category: Contract Employee
Primary Location: Hillsboro, OR US
Other Locations: US, Arizona, Phoenix
Job Type: Intel Contract Employee

RF/Analog Physical Designer

Job Description

The Intel NGS team is chartered with developing advanced prototypes of various technologies to deliver innovative and state of the art wireless experiences into the market within the Internet of Things, 5G Next Generation Wearable and IoT solutions and other world-class wireless connectivity technologies and products.

As an RF Physical Design Engineer at Intel, you will be responsible for implementing the physical design layout of the various RF IC blocks working alongside the Circuit Design Engineers and top level layout owner.

Role Responsibilities:

  • Floor-planning and layout of the various RF/analog blocks
  • You will be responsible for the layout and verification of your circuit blocks such as LNAs, mixers, amplifiers, VCOs, Power Amplifiers and other RF and mmWave circuits
  • You would also create custom layouts such as inductor and baluns
  • Verification includes running design rule checks (DRC), schematic-to-layout verification (LVS) and debugging using standard industry tools
  • You would also be required to troubleshoot a wide variety of issues: including but not limited to: ESD, ERC, reliability, meeting density targets, and other HVM related requirements. This requires extensive knowledge and practical application of methodologies and physical design
  • The candidate would also support creation of accurate schedules for planning


Bachelors of Science in Electrical Engineering or related field :

  • 10 + years Cadence Virtuoso Layout experience for high performance analog designs
  • Demonstrated proficiency in ability to fully verify complex analog macros through DRC/ERC/LVS process using industry standard tools
  • Experience laying out advanced RF and mmWave circuit blocks in advanced silicon technologies
  • Ability to work as part of a cross functional team in a dynamic environment

Preferred Qualifications:

  • Fundamental understanding of the submicron, Low Voltage, Low Power CMOS RFIC Design; including common centroid layouts, matching, well isolation, and substrate and tap connections.
  • Proficiency in using Cadence layout tools
  • Experience in Intel and foundry technologies
  • Previous experience in the layout of Op-Amp, bandgap, LDO, IF Filters, VGA, VCO and PLLs
  • Good communication, problem solving and documentation skills

Inside this Business Group

The Next Generation and Standards Group's mission is to lead standards, ecosystem, and prototyping development efforts across Intel for advanced wireless communications IP, starting with 5G and beyond. This group brings together a panorama of competencies including standards creation, ecosystem development, use case and business development in creating advanced prototypes and technologies that propel Intel's leadership. In addition, the group is rapidly expanding towards integration of communications and compute with new technologies and use cases including advanced end to end communication networks, autonomous driving, drones, artificial intelligence, while continuing its leadership in 5G. NGS holds all the advanced communications and compute technology assets to deliver an exciting, converged future at the center of the intelligent data explosion.

Other Locations

US, Arizona, Phoenix

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....

USIntel Contract EmployeeJR0121899
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