Enabling and validation of various DFT features such as Scan, MBIST, JTAG, etc. for Intel's leading edge SoC designs post Si.
Develops and supports design for test (DFT) structures. Determines design for test approaches and develops DFT architecture. Designs and verifies DFT structures for memories (MBIST), digital and analog circuitry. Performs scan synthesis. Creates, simulates and verifies automatic generated test patterns (ATPG). Creates functional tests and corresponding test patterns. Knows about failure mechanisms in silicon production and creates test algorithms. Supports silicon bring up of test patterns. Performs diagnosis of test patterns on silicon and optimizes test time.
BE/ME with a min exp of 10yrs. in ASIC/DFT and various aspects simulation, Silicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debug In depth knowledge and hands on experience in ATPG, coverage analysis, Transition delay test coverage analysis. Expertise in scripting languages such as perl, shell, etc. is an added advantage Knowledge/experience in post Si debug support Experience in simulating test vectors Working experience in simulation tools like VCS tools Ability to work in an international team, dynamic environmentInside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.