Develops Pre-Silicon DFX validation tests to verify system will meet design requirements. Test generation, coverage improvement, post-silicon debug, vector simulation, Well verse with UVM validation methodology, need to build Test bench to implement monitors, checkers, scoreboard. Subsystem/SoC Val Consultation to bring up and guide teams on DFT features. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing. Measures for failing RTL tests. Analyzes and uses results to modify testing.
BS degree in Electrical Engineering or other related field of study with a minimum of 9+ years of relevant experience in SOC/IP DFT or MS degree with 7+ years of directly related to DFT activities. Experienced in various aspects of DFT - SCAN insertion, ATPG, BSCAN, MBIST. Strong validation background and exposure to pre-silicon validation environment UVM sound communication skills, leadership skills and ability to work with global teams.Inside this Business Group
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.