Come join us in the centralized Design for Test Engineering Group (DTEG) under the Silicon Engineering Group (SEG). We invite you to take an active part in our mission to define strong and robust DFT methodologies and develop state of the art design and verification tooling to drive products development and production effectiveness and decrease their Time-To-Market.
Your responsibilities will include but not be limited to:
-Driving the RTL integration methodology, innovations and productivity improvements in design flow while focusing on all aspects on integration including low power, IP requirements, RTL integration flow, and physical design readiness
-Working with a team of talented engineers in the tools team and SoC/IP design teams Develop and test Engineering Design Automation tools, creates flows/scripts to analyze, and test design methodologies.
-Engaging in front line tool support and advocating in applying design methodologies to help execute projects effectively and successfully with high quality
You must be a BSc/MSc student in Electrical Engineering or Computer Engineering.
Programming experience is an advantage.
The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.