Physical Design Engineer

Job Description
You will be part of IACG group within PEG, in the Big Core IP development team driving Intel's latest CPU's in the latest process technology. Your responsibilities will include but not limited to:
- Layout design of Datapath and Register Files using semi-automated tools, flows, methodology along with manual polygon edits
- Block level/sub-chip level floor-plan, Layout integration, power grid planning, clock routing
- Abstract view generation and full-chip assembly
- RC extraction, RC aware routing both manual and semi-auto
- Coordination with circuit designer
- Reliability Verification (EM/SH/IR, etc)
- Physical verification (DFM, DRC, LVS, Density, Antenna)
- Develop layout design methodologies

Qualifications

Qualifications

You must possess a Master's Degree in VLSI or Electricals or equivalent or a Bachelor's Degree in E&C or Electrical Engineering or equivalent

Knowledge/good understanding on :
- Layout design of high speed Datapath or Register file or custom memory
- Understanding of Layout design Convergence at Block/Section Level
- Basic understanding of timing analysis is plus
- Scripting knowledge is plus
- Strong verbal and written communication skills

Inside this Business Group