SOC DFT engineer
Develops and supports design for test (DFT) structures. Determines design for test approaches and develops DFT architecture. Designs and verifies DFT structures for memories (MBIST), digital and analog circuitry. Performs scan synthesis. Creates, simulates and verifies automatic generated test patterns (ATPG). Creates functional tests and corresponding test patterns. Knows about failure mechanisms in silicon production and creates test algorithms. Supports silicon bring up of test patterns. Performs diagnosis of test patterns on silicon and optimizes test time.
Inside this Business Group
Candidate should possess a Bachelors or Master's degree in Computer/ Electrical/Electronic Engineering with 0-2 years' experience. Strong hands on knowledge of DFT architecture, design, methodologies and tools - Scan, MBIST, Analog DFT, JTAG, Security. Had executed/experienced complete SOC DFT cycle. Excellent scripting, debug & analytic skills. A good team player with excellent interpersonal and communication skills