Inside this Business Group
The applicant should have Bachelor degree in (Electrical & Electronics or Computer Engineering or equivalent) Engineering or higher, and 6-7 years of experience in RTL design and verification.
- Familiarity or experience in RTL design with Verilog and/or VHDL is required.
- Familiarity or experience with RTL verification and timing analysis/closure is required.
- Knowledge of high speed serial system interfaces (such as PCI Express) is a strong plus.
- Familiarity with Perl, C++ and shell scripts is a plus.
- Strong skills in communication, initiative, promote innovation and collaboration.
- Highly motivated to learn and adapt to fast-evolving technologies and environments.