Physical Layout Design Engineer
You will be responsible to deliver a good quality layout which includes the following:
- Working with the circuit design team to plan and schedule work as needed to build a complex analog layout with Intel latest process nodes.
- Running complete sets of design verification tools and completely understanding the LV, RV, ESD, DFM, and other reports.
- Finding the fastest way to complete the layout that meets the stringent matching, performance area, and power requirements.
- Implementing ECO and LCO to meet the design specification and having the ability to create schematics to debug issues/test cases.
- On time delivery to the project schedule without compromise to the layout quality is always the top priority.
Creates bottomsup elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, fullchip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design.
Inside this Business Group
Required 1 to 3+ years' experience in deep SubMicron analog layout design.
- Experience building tight matching, low capacitance, low power analog blocks, resistors, capacitors, high voltage devices, pad IOs, ESD structures, etc.
- Proficient experience with custom and standard cell based floor planning and hierarchical layout assembly.
- Deep understanding of IR drop, RC delay, electro-migration, self-heating and cross capacitance.
- Experience with analog and DFM practices.
- High-level proficiency in interpretation of UNIX environment, Genesys, Calibre, DRC, ERC, LVS, etc. reports.
- Scripting experience in PERL, TCL, Unix or SKILL CODE is considered a plus.