Inside this Business Group
The applicant should have Bachelor degree in (Electrical & Electronics or Computer Engineering or equivalent) Engineering or higher, and 3-5 years of experience in RTL verification and validation.
-Experience in System Verilog, OVM, UVM, RTL model build or testbench development.
-Capable in developing test plans, test contents and coverage points for verification purpose based on high level architecture specification.
-Experience in VLSI or Structural and Physical design flow/methodology.
-Experience in PCI Express or any standard bus protocol would be added value.
-Familiarity or experience in RTL design with Verilog and/or VHDL is a strong plus
-Strong analyzing and debugging skills, and creative in problem solving.
-Strong programming skill in Perl, C++ etc.
-Good communication skill.
-Highly motivated to learn and adapt to fast-evolving technologies and environments.